1. Field of the Invention
The present invention relates to a device for analyzing an AT command which is used in a modem device for personal computer.
2. Description of the Prior Art
The AT command used in a modem device for a personal computer in the prior art automatically recognizes and responds to a communication rate and a communication parameter between a DTE (Data Terminal Equipment) and a DCE (Data Circuit Terminating Equipment).
The AT command is such that the first two characters of the command are limited to xe2x80x98ATxe2x80x99 or xe2x80x98atxe2x80x99, and this is the reason why the AT command is called xe2x80x98ATxe2x80x99 command. What the AT command automatically recognizes and responds to is a communication rate and a communication parameter. An automatically recognizing method therefor will now be described.
Description will be made for the communication rate.
When xe2x80x98Axe2x80x99 or xe2x80x98axe2x80x99 at the first of the command is expressed by ASCII code, xe2x80x98Axe2x80x99 and xe2x80x98axe2x80x99 are expressed by 41h and 61h in hexadecimal notation, respectively. Because the least significant bit (LSB) of each of both is 1, a space (start bit) of one bit certainly appears at the beginning of the communication when each of both is converted into the LSB-first bit series of a serial interface. The communication rate is obtained as a result of measuring the time of this space.
In the times a personal-computer communication using the AT command started, the communication rate was 300 bps. However, the rate increases remarkably after that, to 14400 bps, then, 33600 bps, and, recently, 56000 bps is used. Moreover, the 56000 bps is the communication rate between a DCE and a DCE, and there is a possibility that data therebetween has been compressed to xc2xc at the maximum. Therefore, for communication between a DCE and a DTE, it is necessary to satisfy the communication rate of 230.4 kbps which is the four times resulting from decompressing the thus compressed data. The standard baud rates used are 230400, 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 and 300 bps. A difference in clock occurs between a transmission side and a reception side due to asynchronous communication. However, a frequency error of+2.5% throughxe2x88x921.0% is allowed with respect to a standard frequency at a rule. Therefore, when automatic setting of the rate is performed, it is necessary to detect a rate of reception from the other side, and set a frequency of a baud rate which is nearest to and supports this rate
Description will be made for the above-mentioned communication parameter.
With regard to the communication parameter, 8 bits (the start bit and 7 data bits) are set first without parity bit. The second character (T or t) is received at the communication rate obtained using the first character (A or a). Then, from a parity bit (D7) of each of the first character and second character and whether the characters are AT or at, the communication parameter which ITU-T, V.25ter supports is obtained. FIG. 1 shows these communication parameters. D7 which expresses the parity bit expresses the eighth bit when the respective bits are expressed by D0-D7 in the LSB first manner, these respective bits comprising the 7 data bits and the following parity bit. The communication parameter is also called a data format.
The AT command has been analyzed using a microprocessor unit (MPU) in the prior art. However, because the communication rate has been increased as mentioned above and various functions have come to be used, the load of the MPU has increased. Japanese Laid-Open Patent Application No. 9-153923 discloses an art for reducing the load of the MPU and for automatic recognition of the communication rate using the AT command.
An AT-command analyzing device in the prior art disclosed in Japanese Laid-Open Patent Application No. 9-153923 is shown in FIG. 2, and will now be described.
In FIG. 2, RXD 100 is an input-data signal of a serial interface with a DTE. An analysis-commencement determining portion 101 receives instructions to start communication-rate analysis from a later-described MPU 109, monitors the RXD 100, and sends out a Start signal for rate-measurement commencement. A rate analyzing portion 102 receives the Start signal and analyzes the communication rate of the start bit. A serial-data control portion 103 prevents input of the RXD 100 to a later-described UART (Universal Asynchronous Receiver Transmitter) 108 during the period during which a gate signal output from the rate analyzing portion 102 is in the OFF state.
A decoder 104 generates rate data and frequency-dividing data for generating a baud-rate clock from a count value obtained as a result of the rate analyzing portion 102 counting clock pulses for the communication period of the start bit. A rate register 105 holds the rate data from the decoder 104. A shift-register portion 106 including 8-bit shift register, receives the first character of the AT command, and holds it. A baud-rate clock generating portion 107 receives the frequency-dividing data from the decoder 104, generates the baud-rate clock therefrom for receiving the command, and supplies it to the shift-register portion 106 and UART 108. The UART 108 is a transmission and reception circuit which transmits and receives the RXD 100 which is asynchronous transmission serial data.
The MPU 109 outputs an indicate signal to the analysis-commencement determining portion 101, and gives it the instructions to start communication-rate analysis. The MPU 109 receives the first character from the shift-register portion 106, determines that it is xe2x80x98Axe2x80x99, receives received data starting from the second character and analyzes it. The analysis-commencement determining portion 101 determines that the ON state of the indicate signal from the MPU 109 is the instructions to start communication-rate analysis, and determines that no command has been provided, when a steady state in which the logic (H or 1) inverse to the logic (L or 0) of the start bit continues for more than ten periods of the shift-register clock (corresponding to the total 10 bits of the start, stop bits, parity bit and 7 data bits) in the RXD 100 which has been monitored. Then, the analysis-commencement determining portion 101 causes the Start signal to be in the ON state provided to the rate analyzing portion 102, and causes it to start communication-rate analysis.
The rate analyzing portion 102 causes the gate signal to be in the OFF state, monitors the RXD 100 and waits for the start bit. The serial-data control portion 103 disconnects the UART 108 from the RXD 100 during the period during which the gate signal is in the OFF state, and, thereby, prevents the UART 108 from receiving the first character of the AT command at an erroneous communication rate before the rate is set. When the start bit appears in the RXD 100, the rate analyzing portion 102 causes an internal counter to start, and measures the time of the start bit. Then, when the start bit finishes, the rate analyzing portion 102 causes the internal clock to stop, causes a load signal to be in the ON state, and provides a rate-measurement-completion interrupt signal to the MPU 109.
The rate data includes the value of the rate calculated from the count value of the rate analyzing portion 102 and an error bit which is used, when the rate measurement has ended in failure, to report this matter. The rate register 105 holds the rate data from the decoder 104 at the time the load signal from the rate analyzing portion 102 comes to be in the ON state. The baud-rate-clock generating portion 107 loads therein the frequency-dividing data from the decoder 104 at the time the load signal from the rate analyzing portion 102 comes to be in the ON state, generates a new baud-rate clock based on this frequency dividing data, and supplies it to the UART 108. Thereby, the UART 108 continually has the clock suitable to the communication rate supplied thereto. Further, the baud-rate-clock generating portion 107 supplies the shift-register clock having the same frequency as that of the baud-rate clock for 8 periods thereof to the shift-register portion 106.
The shift-register portion 106 receives the 8 bits including the 7 data bits starting after the start bit of the first character of the command and the parity bit thereof in timing of the shift-register clock supplied from the baud-rate-clock generating portion 107. Then, when reception of the 8 bits has finished, the shift-register portion 106 causes a first-character reception completion signal to be in the ON state, and causes interrupt in the MPU 109. When this reception completion signal has come to be in the ON state, the rate analyzing portion 102 causes the gate signal to be in the ON state. When the gate signal has come to be in the ON state, the RXD 100 is input to the UART 108. Thereby, the UART 108 does not affected by the first character, and, as a result, can receive the second character and the following characters of the AT command positively.
The UART 108 receives the second character and following characters of the AT command in sequence in timing of the baud-rate clock supplied by the baud-rate-clock generating portion 107, and causes reception interrupt in the MPU 109 at every character. When the MPU 109 receives the rate-measurement completion interrupt signal from the rate analyzing portion 102, reads the rate data from the rate register 105, determines from the error bit whether or not the rate measurement has ended successfully, and recognizes the value of the measured rate when the measurement has ended successfully.
Then, when receiving the reception completion interrupt from the shift-register portion 106, the MPU 109 reads the first character of the command and the parity bit thereof, and determines whether the character is xe2x80x98Axe2x80x99 or xe2x80x98axe2x80x99. When the rate measurement ended in failure or the first character is neither xe2x80x98Axe2x80x99 nor xe2x80x98axe2x80x99, the MPU 109 causes the indicate signal to be in the ON state, and performs the rate analysis again from the beginning. The MPU 109 receives the second character and following characters of the AT command through the UART 108. After receiving the reception interrupt from the UART 108, the MPU 109 reads the received data, and determines the data format of the received data from the parity bit of the first character and the parity bit of the second character when the second character is xe2x80x98Txe2x80x99 or xe2x80x98txe2x80x99. The MPU 109 sets the UART 108 in this data format, and the UART 108 receives the third character and following characters of the AT command in sequence.
In the above-described AT-command analyzing device in the prior art, in addition to the transmitting and receiving means (UART) 108 and control means (MPU) 109, the rate analyzing portion 102 which analyzes the communication rate in response to the instructions from the MPU 109, the baud-rate-clock generating portion 107 which generates the baud-rate clock from the analyzed communication rate, transmits it to the UART 108 and reports the communication rate, and the shift-register portion 106 which inputs thereto this baud-rate clock and receives the first character are provided. Thereby, such functions as those of analyzing the communication rate, reporting of the communication rate to the UART 108, receiving the first character, which have been performed by the MPU 109 in the further prior art, are performed by the peripheral circuits such as the rate analyzing portion 102, baud-rate-clock generating portion 107, shift-register portion 106 and so forth. As a result, the load of the MPU 109 is reduced.
As described above, in this prior art, in order to reduce the load of the MPU which recognizes the AT command and controls a modem, hardware is used for performing all the functions ended at the generation of the baud rate.
Because the communication rate has been increased, the method of performing the analysis of the rate of the AT command and setting of the baud rate not by the MPU but by the peripheral hardware circuits is used in this prior art. However, it is necessary to support many rates of 300 through 230.5 kbps. Therefore, in comparison to the control method using software of the MPU in the further prior art, the circuit control for the AT-command analysis is needed, the decoding circuit for determining the baud rate is needed, and so forth. Thereby, the circuit arrangement is complicated, and the size of the circuit is large.
Further, the baud rate of the UART 108 is output from the baud-rate-clock generating portion 107, and is reset only after the rate of the AT command is analyzed. In this arrangement, in a case where the AT command is not received, for example, in a case where a ring of telephone comes, when the modem detects it, the modem needs to send the characters of the ring to the DTE. In this case, the MPU 109 needs to set the UART 108 in a baud rate which has been set using an internal parameter, and to cause the UART 108 to operate. However, these functions cannot be performed in the above-described method in the prior art.
Further, with regard to the first character, the character is checked by the MPU after the 8 bits are sampled. When the first character is neither xe2x80x98Axe2x80x99 nor xe2x80x98axe2x80x99, it is necessary to receive the subsequent character as the first character. However, in a case of high-rate data, this determination may be delayed due to use of software, and, thereby, there is a possibility that the subsequent character cannot be received properly. Further, in asynchronous communication, when an abnormal frame character which does not have the stop bit is generated, because the stop bit is not checked in this prior art, it is not possible to recognize this character to be an erroneous character.
The present invention has been devised in consideration of the above-described problems. An object of the present invention is to reduce the size and complexity of the peripheral circuit when the rate of the AT command is analyzed. Another object of the present invention is to provide an error detecting function for immediately detecting the error that the first character is neither xe2x80x98Axe2x80x99 nor xe2x80x98axe2x80x99.
Further, another object of the present invention is to enable using of a circuit provided for analyzing the rate of the AT command as a circuit for performing another function in a modem, and, thereby, to prevent increase in size of the entire circuit.
An AT-command analyzing device, according to the present invention, comprises:
a transmitting and receiving portion (UART 6) which receives asynchronous transmission serial data based on a baud-rate clock from a DTE;
a control portion (MPU 9) which analyzes the data received by the transmitting and receiving portion;
a baud-rate generating portion (8) which generates the baud-rate clock to be output to the transmitting and receiving portion in accordance with instructions from the control portion;
a measuring portion (first counter 1) which measures the span of the start bit of the first character of an AT command transmitted from the DTE based on instructions from the control portion;
a rate analyzing portion (decoder 2) which receives a measurement result of the measuring portion, outputs frequency-dividing data for producing a clock for sampling the first character, and also outputs, when the rate of the start bit is more than a preset value, a flag indicating this matter;
a sampling-clock generating portion (second counter 3) which selects, in accordance with whether or not the flag is present, the frequency-dividing data from either the rate analyzing portion or the control portion, and produces a sampling clock; and
a shift-register portion (shift register 5) which, as a result of the flag being present or instructions being provided from the control portion, receives data subsequent to the start bit of the first character based on the sampling clock from the sampling-clock generating portion, and holds the received data, which data is then read by the control portion.
It is preferable that the shift-register portion checks, each time when sampling a bit, whether or not the first character is xe2x80x98Axe2x80x99 or xe2x80x98axe2x80x99 which corresponds to 41H or 61H in hexadecimal notation, and, when determining that the first character is neither xe2x80x98Axe2x80x99 nor xe2x80x98axe2x80x99, stops the sampling operation and outputs a flag indicating an error to the control means.
Further, it is preferable that the shift-register portion stops a sampling operation when, before sampling a bit subsequent to the start bit, the level of the received data of the bit subsequent to the start bit changes from high to low, and outputs a flag indicating an error to the control means.
Furthermore, it is preferable that the shift-register portion attempts to sample, after sampling the 8 bits subsequent to the start bit, the following stop bit, and, when being not able to detect the stop bit, outputs a flag indicating an error to the control means.
Further, it is possible that the sampling-clock generating portion can operate in a one-shot-pulse outputting operation mode other than a sampling-clock generating mode, whether the sampling-clock generating portion operates in the one-shot-pulse outputting operation mode or the sampling-clock generating mode can be determined in accordance with instructions from the control portion, and the sampling-clock generating portion can output a one-shot pulse as an interrupt signal of the control portion in the one-shot-pulse outputting operation mode.
As described above, in the AT-command analyzing device according to the present invention, setting of the baud rate of the transmitting and receiving portion (UART) after the analysis of the rate of the AT command and so forth are performed by the control portion (MPU). Based on the count value obtained from measuring the span of the start bit, the clock rate of the sampling clock for sampling the first character of the AT command is automatically set by the peripheral circuits or set by the control portion (MPU). Whether the clock rate of the sampling clock for sampling the first character of the AT command is automatically set by the peripheral circuits or set by the control portion (MPU) is determined from the rate of the AT command obtained based on the count value resulting from measurement of the span of the start bit.
According to the present invention, in comparison with the prior art in which all the operations are performed through the circuit control, because the analysis of the rate of the AT command, which rate is so low that the rate can be analyzed through control by the software of the control portion (MPU) sufficiently, and the setting of clock generation for sampling the first character of the AT command performed after that are performed by the software of the control portion (MPU). On the other hand, the analysis of the rate of the AT command, which rate is so high that the rate analysis cannot be controlled by the software of the control portion (MPU) sufficiently, and the setting of clock generation for sampling the first character of the AT command performed after that are performed by the peripheral circuits. Thereby, it is possible to reduce the size and complexity of the entire circuit.